encounter里将设计变为macro cell的方法( Turn a design into macro cell in Encounter )

在SoC设计中，某些功能可能重复使用，此时，除采用层次化设计方法[1]以外。也可以将这些做好的功能块生成macro cell，用于顶层模块。其原理和处理memory generator生成的cache是一样的。

Some functions may be repeatedly used in SoC design. At this time, besides hierarchical design method[1], we can also generate macro cells for these function unit designs and use them in constructing the top cell.

[1]. http://www.cadence.com/community/blogs/di/archive/2008/11/06/demo-partitioning-a-design-in-soc-encounter.aspx

首先，将功能模块从网表中分离出来，使用传统后端流程实现，signoff后使用savemodel命令存出lef格式。

First, partition the function model from the netlist and implement it using traditional backend flow. After signoff, you can save the lef file using savemodel command.

savemodel -signoff -outDir modelname

其中，-signoff表示保存的是signoff后的设计，也可以使用-preCTS, -postCTS, -postRoute。-outDir表示存储设计的目录。其中-postRoute会生成.lib文件，供顶层设计使用。
在得到.lib文件之前要用timeDesign命令生成时序约束。

where -signoff specifies that the design is after signoff, you can also use -preCTS, -postCTS or -postRoute. The saving directory is specified by -outDir. The option -postRoute can be used to generate .lib file for top design.
You have to use timeDesign to generate timing constraints before generating .lib file.

timeDesign -postRoute -outDir

接下来，我们假设这个模块被使用了两次，中间用Bus连接。网表是这么写的：

Then, we assume that this module is used twice and connected with Bus in the top design. The netlist is written as:

module chip_top(
input ...
output ...
);

wire ...

IP north_block();
IP south_block();

end module

我们读入网表，并使用placeInstance命令来进行布局，格式为

We can import the netlist and then floorplan using command: placeInstance. i.e.

placeInstance [] [-fixed | -placed]
placeInstance north_block 3 3 R180 -fixed

如果想翻转macro，可以采用flipInst来翻转macro，格式为

If you want to flip macro, you can use command flipInst. i.e.

flipInst {MX | MY}

最后，使用同样的后端流程，即可完成一个bottom-up的顶层设计。

You can use the same backend flow now to complete a bottom-up top design.