encounter的自顶向下层次设计流程（top-down hierarchical design flow by encounter）

在这里举一个自顶向下流程的实例。假设netlist里例化了一个模块两次：

There is an example about top-down flow here. Suppose that a module has been instantiated for 2 times:

CS_router north_router( );
CS_router south_router( );

我们可以读入这个网表，选中所有标准单元，然后采用菜单里的partition -> specify partition进行自顶向下层次划分，与网表一致，默认分为两组。每组单元的位置和大小都可以调整。

After importing the netlist, we can select all the standard cells and create a top-down hierarchical partition by menu-> partition -> specify partition. These cells will be divided as in the netlist. The location and size of these cells can be adjusted.

此时我们可以对每组里面的标准单元进行布局，选中要布局的单元组，使用Place->Standard Cells，然后用一个粗略的布局选项Run placement in floorplan mode完成布局。记得preplace optimization和in place optimization都得选上。

Now we can place the standard cells in a partitioned group. Select one and use menu-> place -> standard cells, then select a rough place option "Run placement in floorplan mode" to complete. Remember that you have to select both preplace and in place optimization options.

使用Partition菜单的derive timing budgets来存timing model，然后用commit partition确定Block。之后退出encounter，打开conf文件，读取floorplan和placement信息，即可修改这个被分割的Block了。

We can use menu -> partition -> derive timing budgets to save .lib timing model and the commit partition. Then we exit encounter, open the saved conf file and read floorplan & placement information. The partitioned block can be optimized isolately.

encounter里将设计变为macro cell的方法( Turn a design into macro cell in Encounter )

在SoC设计中，某些功能可能重复使用，此时，除采用层次化设计方法[1]以外。也可以将这些做好的功能块生成macro cell，用于顶层模块。其原理和处理memory generator生成的cache是一样的。

Some functions may be repeatedly used in SoC design. At this time, besides hierarchical design method[1], we can also generate macro cells for these function unit designs and use them in constructing the top cell.

[1]. http://www.cadence.com/community/blogs/di/archive/2008/11/06/demo-partitioning-a-design-in-soc-encounter.aspx

首先，将功能模块从网表中分离出来，使用传统后端流程实现，signoff后使用savemodel命令存出lef格式。

First, partition the function model from the netlist and implement it using traditional backend flow. After signoff, you can save the lef file using savemodel command.

savemodel -signoff -outDir modelname

其中，-signoff表示保存的是signoff后的设计，也可以使用-preCTS, -postCTS, -postRoute。-outDir表示存储设计的目录。其中-postRoute会生成.lib文件，供顶层设计使用。
在得到.lib文件之前要用timeDesign命令生成时序约束。

where -signoff specifies that the design is after signoff, you can also use -preCTS, -postCTS or -postRoute. The saving directory is specified by -outDir. The option -postRoute can be used to generate .lib file for top design.
You have to use timeDesign to generate timing constraints before generating .lib file.

timeDesign -postRoute -outDir

接下来，我们假设这个模块被使用了两次，中间用Bus连接。网表是这么写的：

Then, we assume that this module is used twice and connected with Bus in the top design. The netlist is written as:

module chip_top(
input ...
output ...
);

wire ...

IP north_block();
IP south_block();

end module

我们读入网表，并使用placeInstance命令来进行布局，格式为

We can import the netlist and then floorplan using command: placeInstance. i.e.

placeInstance [] [-fixed | -placed]
placeInstance north_block 3 3 R180 -fixed

如果想翻转macro，可以采用flipInst来翻转macro，格式为

If you want to flip macro, you can use command flipInst. i.e.

flipInst {MX | MY}

最后，使用同样的后端流程，即可完成一个bottom-up的顶层设计。

You can use the same backend flow now to complete a bottom-up top design.

encounter io assignment file 的写法(generation)

Author：Lian Duan
作者：段炼

此文用于SoC Encounter 7.1，也可供其他版本的使用者参考。

This article is written for SoC Encounter 7.1 , and it can also be a reference for users of other encounter version.

环境：使用了ST microelectronics的45nm库，由于它给高校的LEF文件不全，我使用OSU的45nm实验库做了补全，层数改为1p7m(layer: 1 poly 7 metal)。

Environment: I use the 45nm library from ST microelectronics. The LEF file of this library is not complete so I combine it with another LEF file written by OSU. The library has been modified to be 1p7m(layer: 1 poly 7 metal).

当我们导入网表时，可以设置io assignment file，很多朋友找不到相关帮助文件在什么地方，如果你用的是cadence 2008，你可以在./soc71/doc/soceUG目录下找到soceUG.pdf这个文件。然后搜索"assignment"关键字即可。

When we import our netlist, we can set the io assignment file. Someone may have difficulties to find the help documents. It is under the directory ./soc71/doc/soceUG if you are using cadence 2008. You can open the file soceUG.pdf in that directory and search for keyword "assignment".

写好的io文件可以用Design -> Load -> I/O File导入，但Design -> Import Design -> I/O Assignment File不支持此格式，怀疑后者还是只认老版本的格式。

The io file can be imported by menu: Design -> Load -> I/O File, but it can not be import by menu: Design -> Import Design -> I/O

(globals
version = 3
io_order = default
)

其中version 表示I/O format的版本，io_order表示排列次序，例如default指：水平的边，从左到右排，垂直的边，从下往上排。

where version specifies the version of the I/O format. Io_order specifies the order of I/O pins. This can be clockwise, counterclockwise, or default. The option "default" means: for horizontal edge is from left to right, for vertical edge is from bottom to top.

(iopin
(top
(pin name="N_in" offset=0.2700 layer=2 width=0.0700 depth=0.0700 place_status=placed )
(pin name="N_out" skip=1.3410 layer=2 width=0.0700 depth=0.0700 place_status=placed )
)
(left
)
(right
)
(bottom
)
)

以上是.io文件的正文示例。在这里，top等是edge，pin name，layer分别代表pin的名称和金属层，width和depth是pin的宽和长。offset和skip分别表示绝对偏移量和间距，以μm为单位。

This is the example io file. Top, ...etc, is the edge of chip. Pin name and layer specify the name and metal of the pin. Width, depth specify the size of the pin. Offset and skip specify the offsets and distance of the pins in μmeters, respectively.

写好的io文件在Floorplan以后导入，即可获得想要的io pin排列。

We should import io file after floorplan and the specified arrangement of io pins will be achieved.